(1) Field of The Invention
This invention relates to a random access memory device and, more particularly, to a method of fabricating a three-dimensional stacked capacitors having increased capacitance.
(2) Description of The Prior Art
Very large scale integration (VLSI) semiconductor technologies have dramatically increased the circuit density on the chip. The miniaturized devices built in and on the semiconductor substrate, making up these circuits are very closely spaced and their packing density has increased significantly. Future requirements for even greater increases in packing density is putting additional demand on the semiconductor technologies and more particularly on the photolithographic techniques.
The dynamic random access memory (DRAM) chip having an array of charge storage cells is one circuit type that is experiencing increasing demand for higher packing density. These individual DRAM storage cells, consisting usually of a single metal-oxide-semiconductor field-effect transistor (MOSFET) and a single capacitor, are used extensively in the electronics industry for storing data. A single DRAM storage cell stores a bit of data on the capacitor as electrical charge.
However, as the array of cells on the DRAM chip increase in number and the capacitor decrease in size, it becomes increasingly difficult to maintain sufficient charge on the storage capacitor to maintain an acceptable signal-to-noise level. Also, these volatile storage cells require more frequent refresh cycles in order to retain their charge.
These storage capacitors are formed either in the substrate, usually referred to as trench capacitors, or by forming stacked capacitors on the substrate after first fabricating the field effect transistors. The latter method has received considerable attention in recent years. However, since each capacitor in the array of storage cells are confined within the cell area, it is difficult to maintain sufficient capacitance as the cell size decreases. Therefore, it becomes necessary to explore other methods for increasing the capacitance.
Some methods for increasing capacitance include building a three dimensional capacitor structure extending vertically upward over the cell area. For example, see H-H Tseng U.S. Pat No. 5,192,702 and U.S. Pat. No. 5,126,916 and C. H. Dennison et al U.S. Pat. No. 5,061,650. Others have utilized sidewall techniques to build vertical capacitor structures, such as described by P. Fazan et al in U.S. Pat. No. 5,084,405 and S Matsumoto et al U.S. Pat. No. 5,217,914. Another approach is to roughen the surface of the bottom electrode of the capacitor to effectively increase the surface area without increasing its overall size. For example, see H. C. Tuan et al U.S. Pat. No. 5,266,514. Another technique for increasing the surface area by forming a villus-type capacitor is described by J. Ahn in U.S. Pat. No. 5,158,905 and a technique for forming a porous structure is described by J. Ko in U.S. Pat. No. 5,227,322. Still another approach is to use inter-electrode insulators having high dielectric constants. For example see the publication "A Newly Designed Planar Stacked Capacitor Cell with High Dielectric Constant Film for 256 Mbit DRAM" by T. Eimori et al IEEE International Electron Device Meeting Proceedings, Dec. 1993 pages 631-634.
Although there has been considerable work done to increase the capacitance area on these very small storage capacitors, it is still desirable to further improve these capacitors while retaining as simple a process as possible to maintain high chip yields, low cost and good reliability. This is especially true as the DRAM increase to 256 Mbits on a chip.